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24-Lane 3-Port Non-Transparent PCI Express(R) Switch
(R)
89HPES24NT3 Data Sheet
Preliminary Information*
Device Overview
The 89HPES24NT3 is a member of the IDT PRECISETM family of PCI Express(R) switching solutions offering the next-generation I/O interconnect standard. The PES24NT3 is a 24-lane, 3-port peripheral chip that performs PCI Express Base switching with a feature set optimized for high performance applications such as servers, storage, and communications/networking. It provides high-performance switching functions between a PCIe(R) upstream port, a transparent downstream port, and a non-transparent downstream port. With non-transparent bridging (NTB) functionality, the PES24NT3 can be used standalone or as a chipset with IDT PCIe System Interconnect Switches in multi-host and intelligent I/O applications such as communications, storage, and blade servers where inter-domain communication is required.
Features
High Performance PCI Express Switch - Twenty-four PCI Express lanes (2.5Gbps), three switch ports - Delivers 96 Gbps (12 GBps) of aggregate switching capacity - Low latency cut-through switch architecture - Support for Max Payload size up to 2048 bytes - Supports one virtual channel and eight traffic classes - PCI Express Base specification Revision 1.0a compliant
Flexible Architecture with Numerous Configuration Options - Port arbitration schemes utilizing round robin - Supports automatic per port link width negotiation (x8, x4, x2, or x1) - Static lane reversal on all ports - Automatic polarity inversion on all lanes - Supports locked transactions, allowing use with legacy software - Ability to load device configuration from serial EEPROM - Ability to control device via SMBus Non-Transparent Port - Crosslink support on NTB port - Four mapping windows supported * Each may be configured as a 32-bit memory or I/O window * May be paired to form a 64-bit memory window - Interprocessor communication * Thirty-two inbound and outbound doorbells * Four inbound and outbound message registers * Two shared scratchpad registers - Allows up to sixteen masters to communicate through the nontransparent port - No limit on the number of supported outstanding transactions through the non-transparent bridge - Completely symmetric non-transparent bridge operation allows similar/same configuration software to be run - Supports direct connection to a transparent or non-transparent port of another switch
Block Diagram
3-Port Switch Core
Frame Buffer Route Table Port Arbitration Scheduler
Transaction Layer Data Link Layer
Transaction Layer Data Link Layer
Transaction Layer Data Link Layer
NonTransparent Bridge
Multiplexer / Demultiplexer
Phy Logical Layer Phy Logical Layer Phy Logical Layer
Multiplexer / Demultiplexer
Phy Logical Layer Phy Logical Layer Phy Logical Layer
Multiplexer / Demultiplexer
Phy Logical Layer Phy Logical Layer Phy Logical Layer
...
...
...
SerDes
SerDes
SerDes
SerDes
SerDes
SerDes
SerDes
SerDes
SerDes
24 PCI Express Lanes x8 Upstream Port and Two x8 Downstream Ports
Figure 1 Internal Block Diagram
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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(c) 2007 Integrated Device Technology, Inc. *Notice: The information in this document is subject to change without notice
April 11, 2007
DSC 6925
IDT 89HPES24NT3 Data Sheet
Highly Integrated Solution - Requires no external components - Incorporates on-chip internal memory for packet buffering and queueing - Integrates twenty-four 2.5 Gbps embedded full duplex SerDes, 8B/10B encoder/decoder (no separate transceivers needed) Reliability, Availability, and Serviceability (RAS) Features - Upstream port can be dynamically swapped with non-transparent downstream port to support failover applications - Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) - Supports ECRC pass-through in transparent and non-transparent ports - Supports Hot-Swap Power Management - Supports PCI Power Management Interface specification, Revision 1.1 (PCI-PM) - Unused SerDes are disabled Testability and Debug Features - Built in SerDes Pseudo-Random Bit Stream (PRBS) generator - Ability to read and write any internal register via the SMBus - Ability to bypass link training and force any link into any mode - Provides statistics and performance counters Two SMBus Interfaces - Slave interface provides full access to all software-visible registers by an external SMBus master - Master interface provides connection for an optional serial EEPROM used for initialization - Master interface is also used by an external Hot-Plug I/O expander - Master and slave interfaces may be tied together so the switch can act as both master and slave Eight General Purpose Input/Output pins Packaged in 27x27mm 420-ball BGA with 1mm ball spacing
Classes (TCs) and one Virtual Channel (VC) with sophisticated resource management. This includes round robin port arbitration, guaranteeing bandwidth allocation and/or latency for critical traffic classes in applications such as high throughput 10 GbE I/Os, SATA controllers, and Fibre Channel HBAs. Switch Configuration The PES24NT3 is a three port switch that contains 24 PCI Express lanes. Each of the three ports is statically allocated 8 lanes with ports labeled as A, B and C. Port A is the upstream port, port B is the transparent downstream port, and port C is the non-transparent downstream port. During link training, link width is automatically negotiated. Each PES24NT3 port is capable of independently negotiating to a x8, x4, x2 or x1 width. Thus, the PES24NT3 may be used in virtually any three port switch configuration (e.g., {x8, x8, x8}, {x4, x4, x4}, {x4, x2, x1}, etc.). The PES24NT3 supports static lane reversal. For example, lane reversal for upstream port A may be configured by asserting the PCI Express Port A Lane Reverse (PEALREV) input signal or through serial EEPROM or SMBus initialization. Lane reversal for ports B and C may be enabled via a configuration space register, serial EEPROM, or the SMBus.
Product Description Utilizing standard PCI Express interconnect, the PES24NT3 provides the most efficient high-performance I/O connectivity solution for applications requiring high throughput, low latency, and simple board layout with a minimum number of board layers. With support for non-transparent bridging, the PES24NT3, as a standalone switch or as a chipset with IDT PCIe System Interconnect Switches, enables multi-host and intelligent I/O applications requiring inter-domain communication. The PES24NT3 provides 96 Gbps (12 GBps) of aggregated, full-duplex switching capacity through 24 integrated serial lanes, using proven and robust IDT technology. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specification 1.0a. The PES24NT3 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification Revision 1.0a. The PES24NT3 can operate either as a store and forward or cut-through switch depending on the packet size and is designed to switch memory and I/O transactions. It supports eight Traffic
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*Notice: The information in this document is subject to change without notice
April 11, 2007
IDT 89HPES24NT3 Data Sheet
CPU
PES24NT3
CPU
PES24NT3
CPU
PES24NT3
PCIe System Interconnect Switch
PCIe System Interconnect Switch
Embedded CPU
Embedded CPU SATA / SAS
Embedded CPU GbE / 10GigE
FC
Figure 2 PCIe System Interconnect Architecture Block Diagram
Controller 1
CPU
Controller 2
CPU
PES24N3
Cache Maint. & Possible Data Flow x8 PCIe x8 PCIe
PES24N3
x8 PCIe
FC Controller
FC Controller
Storage To Server
FC 2Gb/s and
4Gb/s
FC 2Gb/s and
4Gb/s
To Server
Figure 3 Dual Host Storage System
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IDT 89HPES24NT3 Data Sheet
Pin Description
The following tables list the functions of the pins provided on the PES24NT3. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an "N" are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Signal PEALREV
Type I
Name/Description PCI Express Port A Lane Reverse. When this bit is asserted, the lanes of PCI Express Port A are reversed. This value may be overridden by modifying the value of the PALREV bit in the PA_SWCTL register. PCI Express Port A Serial Data Receive. Differential PCI Express receive pairs for port A. PCI Express Port A Serial Data Transmit. Differential PCI Express transmit pairs for port A PCI Express Port B Lane Reverse. When this bit is asserted, the lanes of PCI Express Port B are reversed. This value may be overridden by modifying the value of the PBLREV bit in the PA_SWCTL register. PCI Express Port B Serial Data Receive. Differential PCI Express receive pairs for port B. PCI Express Port B Serial Data Transmit. Differential PCI Express transmit pairs for port B PCI Express Port C Lane Reverse. When this bit is asserted, the lanes of PCI Express Port C are reversed. This value may be overridden by modifying the value of the PCLREV bit in the PA_SWCTL register. PCI Express Port C Serial Data Receive. Differential PCI Express receive pairs for port C. PCI Express Port C Serial Data Transmit. Differential PCI Express transmit pairs for port C PCI Express Reference Clock. Differential reference clock pair input. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic and on-chip SerDes. The frequency of the differential reference clock is determined by the REFCLKM signal. PCI Express Reference Clock Mode Select. These signals select the frequency of the reference clock input. 0x0 - 100 MHz 0x1 - 125 MHz Table 1 PCI Express Interface Pins
PEARP[7:0] PEARN[7:0] PEATP[7:0] PEATN[7:0 PEBLREV
I O I
PEBRP[7:0] PEBRN[7:0] PEBTP[7:0] PEBTN[7:0] PECLREV
I O I
PECRP[7:0] PECRN[7:0] PECTP[7:0] PECTN[7:0] PEREFCLKP[1:0] PEREFCLKN[1:0]
I O I
REFCLKM
I
Signal MSMBADDR[4:1] MSMBCLK
Type I I/O
Name/Description Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is loaded. Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus. It is active and generating the clock only when the EEPROM or I/O Expanders are being accessed. Master SMBus Data. This bidirectional signal is used for data on the master SMBus. Table 2 SMBus Interface Pins (Part 1 of 2)
MSMBDAT
I/O
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IDT 89HPES24NT3 Data Sheet Signal SSMBADDR[5,3:1] SSMBCLK SSMBDAT Type I I/O I/O Name/Description Slave SMBus Address. These pins determine the SMBus address to which the slave SMBus interface responds. Slave SMBus Clock. This bidirectional signal is used to synchronize transfers on the slave SMBus. Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus. Table 2 SMBus Interface Pins (Part 2 of 2)
Signal GPIO[0]
Type I/O
Name/Description General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PEBRSTN Alternate function pin type: Output Alternate function: Reset output for downstream port B General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PECRSTN Alternate function pin type: Output Alternate function: Reset output for downstream port C General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PALINKUPN Alternate function pin type: Output Alternate function: Port A link up status output General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PBLINKUPN Alternate function pin type: Output Alternate function: Port B link up status output General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: PCLINKUPN Alternate function pin type: Output Alternate function: Port C link up status output General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: FAILOVERP Alternate function pin type: Input Alternate function: NTB upstream port failover General Purpose I/O. This pin can be configured as a general purpose I/O pin. General Purpose I/O. This pin can be configured as a general purpose I/O pin. Table 3 General Purpose I/O Pins
GPIO[1]
I/O
GPIO[2]
I/O
GPIO[3]
I/O
GPIO[4]
I/O
GPIO[5]
I/O
GPIO[6] GPIO[7]
I/O I/O
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IDT 89HPES24NT3 Data Sheet
Signal CCLKDS
Type I
Name/Description Common Clock Downstream. When the CCLKDS pin is asserted, it indicates that a common clock is being used between the downstream device and the downstream port. Common Clock Upstream. When the CCLKUS pin is asserted, it indicates that a common clock is being used between the upstream device and the upstream port. Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus should operate at 100 KHz instead of 400 KHz. This value may not be overridden. Non-Transparent Bridge Reset. Assertion of this signal indicates a reset on the external side of the non-transparent bridge. This signal is only used when the switch mode selects a non-transparent mode and has no effect otherwise. Fundamental Reset. Assertion of this signal resets all logic inside the PES24NT3 and initiates a PCI Express fundamental reset. Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the PES24NT3 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device operation begins. The device exits the reset state when the RSTHALT bit is cleared in the PA_SWCTL register by an SMBus master. Switch Mode. These configuration pins determine the PES24NT3 switch operating mode. 0x0 - Reserved 0x1 - Reserved 0x2 - Non-transparent mode 0x3 - Non-transparent mode with serial EEPROM initialization 0x4 - Non-transparent failover mode 0x5 - Non-transparent failover mode with serial EEPROM initialization 0x6 through 0xF - Reserved Table 4 System Pins
CCLKUS
I
MSMBSMODE
I
PENTBRSTN
I
PERSTN RSTHALT
I I
SWMODE[3:0]
I
Signal JTAG_TCK
Type I
Name/Description JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle. JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG Controller. Table 5 Test Pins (Part 1 of 2)
JTAG_TDI
I
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IDT 89HPES24NT3 Data Sheet Signal JTAG_TDO Type O Name/Description JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated. JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller. JTAG Reset. This active low signal asynchronously resets the boundary scan logic and JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board Table 5 Test Pins (Part 2 of 2)
JTAG_TMS JTAG_TRST_N
I I
Signal VDDCORE VDDIO VDDPE VDDAPE VTTPE VSS
Type I I I I I I
Name/Description Core VDD. Power supply for core logic. I/O VDD. LVTTL I/O buffer power supply. PCI Express Digital Power. PCI Express digital power used by the digital power of the SerDes. PCI Express Analog Power. PCI Express analog power used by the PLL and bias generator. PCI Express Termination Power. Ground. Table 6 Power and Ground Pins
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IDT 89HPES24NT3 Data Sheet
Pin Characteristics
Note: Some input pads of the PES24NT3 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption.
Function PCI Express Interface
Pin Name PEALREV PEARN[7:0] PEARP[7:0] PEATN[7:0] PEATP[7:0] PEBLREV PEBRN[7:0] PEBRP[7:0] PEBTN[7:0] PEBTP[7:0] PECLREV PECRN[7:0] PECRP[7:0] PECTN[7:0] PECTP[7:0] PEREFCLKN[1:0] PEREFCLKP[1:0] REFCLKM
Type I I I O O I I I O O I I I O O I I I I I/O I/O I I/O I/O I/O I I I I I I I
Buffer LVTTL CML
I/O Type Input Serial link
Internal Resistor pull-down
Notes
LVTTL CML
Input Serial link
pull-down
LVTTL CML
Input Serial link
pull-down
LVPECL/ CML LVTTL LVTTL
Diff. Clock Input Input Input STI Input STI pull-up pull-down pull-up
Refer to Table 8
SMBus
MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT
General Purpose I/O System Pins
GPIO[7:0] CCLKDS CCLKUS MSMBSMODE PENTBRSTN PERSTN RSTHALT SWMODE[3:0]
LVTTL LVTTL
Input, High Drive Input
pull-up pull-up pull-up pull-down
pull-down pull-up
Table 7 Pin Characteristics (Part 1 of 2)
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IDT 89HPES24NT3 Data Sheet Function JTAG Pin Name JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N Type I I O I I Low Drive STI pull-up pull-up External pull-down Buffer LVTTL I/O Type STI Internal Resistor pull-up pull-up Notes
Table 7 Pin Characteristics (Part 2 of 2)
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IDT 89HPES24NT3 Data Sheet
Logic Diagram -- PES24NT3
Reference Clocks
PEREFCLKP PEREFCLKN REFCLKM
2 2
PEALREV PEARP[0] PEARN[0]
PEATP[0] PEATN[0] PEATP[1] PEATN[1]
...
PCI Express Switch SerDes Input Port A
PEARP[1] PEARN[1]
PCI Express Switch SerDes Output Port A
...
PEARP[7] PEARN[7]
PEATP[7] PEATN[7]
PEBLREV PEBRP[0] PEBRN[0]
PEBTP[0] PEBTN[0] PEBTP[1] PEBTN[1]
...
PCI Express Switch SerDes Input Port B
PEBRP[1] PEBRN[1]
PCI Express Switch SerDes Output Port B
...
PEBRP[7] PEBRN[7]
PEBTP[7] PEBTN[7]
PECLREV PECRP[0] PECRN[0]
PES24NT3
PECTP[0] PECTN[0] PECTP[1] PECTN[1]
...
PCI Express Switch SerDes Input Port C
PECRP[1] PECRN[1]
PCI Express Switch SerDes Output Port C
...
PECRP[7] PECRN[7]
PECTP[7] PECTN[7]
Master SMBus Interface
MSMBADDR[4:1] MSMBCLK MSMBDAT
4
8
GPIO[7:0]
General Purpose I/O
Slave SMBus Interface
SSMBADDR[5,3:1] SSMBCLK SSMBDAT
4
JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N
JTAG
PENTBRSTN MSMBSMODE CCLKDS CCLKUS RSTHALT PERSTN PENTBRSTN SWMODE[3:0]
4
System Functions
VDDCORE VDDIO VDDPE VDDAPE VSS VTTPE
Power/Ground
Figure 4 PES24NT3 Logic Diagram
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IDT 89HPES24NT3 Data Sheet
System Clock Parameters
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 12 and 13.
Parameter RefclkFREQ RefclkDC2 TR, TF VSW Tjitter
1.
Description Input reference clock frequency range Duty cycle of input clock Rise/Fall time of input clocks Differential input voltage swing4 Input clock jitter (cycle-to-cycle)
Min 100 40
Typical
Max 1251
Unit MHz % RCUI3 V ps
50
60 0.2*RCUI
0.6
1.6 125
Table 8 Input Clock Requirements
The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM. must be AC coupled. Use 0.01 -- 0.1 F ceramic capacitors. RCUI (Reference Clock Unit Interval) refers to the reference clock period. AC coupling required.
2. ClkIn 3. 4.
AC Timing Characteristics
Parameter PCIe Transmit UI TTX-EYE TTX-EYE-MEDIAN-toMAX-JITTER
Description
Min1
Typical1
Max1
Units
Unit Interval Minimum Tx Eye Width Maximum time between the jitter median and maximum deviation from the median D+ / D- Tx output rise/fall time Minimum time in idle Maximum time to transition to a valid Idle after sending an Idle ordered set Maximum time to transition from valid idle to diff data Transmitter data skew between any 2 lanes
399.88 0.7
400 .9
400.12
ps UI
0.15 50 50 20 20 500 1300 90
UI ps UI UI UI ps
TTX-RISE, TTX-FALL TTX- IDLE-MIN TTX-IDLE-SET-TOIDLE
TTX-IDLE-TO-DIFFDATA
TTX-SKEW PCIe Receive UI TRX-EYE (with jitter) TRX-EYE-MEDIUM TO
MAX JITTER
Unit Interval Minimum Receiver Eye Width (jitter tolerance) Max time between jitter median & max deviation Unexpected Idle Enter Detect Threshold Integration Time Lane to lane input skew
399.88 0.4
400
400.12
ps UI
0.3 10 20
UI ms ns
TRX-IDLE-DET-DIFFENTER TIME
TRX-SKEW
1.
Table 9 PCIe AC Timing Characteristics
Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1
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IDT 89HPES24NT3 Data Sheet
Signal GPIO GPIO[7:0]1
1. 2.
Symbol
Reference Min Max Unit Edge
Timing Diagram Reference
Tpw_13b2
None
50
--
ns
Table 10 GPIO AC Timing Characteristics
GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. The values for this symbol were determined by calculation, not by testing.
Signal JTAG JTAG_TCK
Symbol
Reference Edge
Min
Max
Unit
Timing Diagram Reference
Tper_16a Thigh_16a, Tlow_16a
none
50.0 10.0
-- 25.0 -- -- 20 20 --
ns ns ns ns ns ns ns
See Figure 5.
JTAG_TMS1, JTAG_TDI JTAG_TDO
Tsu_16b Thld_16b Tdo_16c Tdz_16c2 Tpw_16d2
JTAG_TCK rising
2.4 1.0
JTAG_TCK falling
-- --
JTAG_TRST_N
1.
none
25.0
Table 11 JTAG AC Timing Characteristics
The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state. The values for this symbol were determined by calculation, not by testing.
2.
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IDT 89HPES24NT3 Data Sheet
Tlow_16a Thigh_16a JTAG_TCK Thld_16b Tsu_16b JTAG_TDI Thld_16b Tsu_16b JTAG_TMS Tdo_16c JTAG_TDO Tpw_16d JTAG_TRST_N Figure 5 JTAG AC Timing Waveform Tdz_16c Tper_16a
Recommended Operating Supply Voltages
Symbol VDDCORE VDDI/O VDDPE VDDAPE VTTPE VSS Parameter Internal logic supply I/O supply except for SerDes LVPECL/CML PCI Express Digital Power PCI Express Analog Power PCI Express Serial Data Transmit Termination Voltage Common ground Minimum 0.9 3.0 0.9 0.9 1.425 0 Table 12 PES24NT3 Operating Voltages Typical 1.0 3.3 1.0 1.0 1.5 0 Maximum 1.1 3.6 1.1 1.1 1.575 0 Unit V V V V V V
Power-Up Sequence
This section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper functionality. For the PES24NT3, the power-up sequence must be as follows: 1. VDDI/O -- 3.3V 2. VDDCore, VDDPE, VDDAPE -- 1.0V 3. VTTPE -- 1.5V When powering up, each voltage level must ramp and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues are avoided. There are no maximum time limitations in ramping to valid power levels. The power-down sequence must be in the reverse order of the power-up sequence.
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IDT 89HPES24NT3 Data Sheet
Recommended Operating Temperature
Grade Commercial Temperature 0C to +70C Ambient
Table 13 PES24NT3 Operating Temperatures
Power Consumption
Typical power is measured under the following conditions: 25C Ambient, 35% total link usage on all ports, typical voltages defined in Table 14. Maximum power is measured under the following conditions: 70C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 14. All power measurements assume that the part is mounted on a 10 layer printed circuit board with 0 LFM airflow.
Number of Connected Lanes: Port-A/Port-B/Port-C
Core (Watts) (1.0V supply) Typ Max
PCIe Digital (Watts) (1.0V supply) Typ Max
PCIe Analog (Watts) (1.0V supply) Typ Max
PCIe Termination (Watts) (1.5V supply) Typ Max
I/O (Watts) (3.3V supply) Typ Max
Total (Watts) Typ Max
8/4/4 8/8/8
0.59 0.68
0.84 0.95
0.75 0.98
1.08 1.43
0.33 0.38
0.42 0.48
0.62 0.88
0.78 1.01
0.002 0.002
0.01 0.01
2.3 2.92
3.12 3.88
Table 14 PES24NT3 Power Consumption
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IDT 89HPES24NT3 Data Sheet
DC Electrical Characteristics
Values based on systems running at recommended supply voltages, as shown in Table 12. Note: See Table 7, Pin Characteristics, for a complete I/O listing.
I/O Type Serial Link Parameter PCIe Transmit VTX-DIFFp-p VTX-DE-RATIO VTX-DC-CM VTX-CM-ACP VTX-CM-DCactive-idle-delta
Description
Min1
Typ1
Max1
Unit
Conditions
Differential peak-to-peak output voltage De-emphasized differential output voltage DC Common mode voltage RMS AC peak common mode output voltage Abs delta of DC common mode voltage between L0 and idle Abs delta of DC common mode voltage between D+ and DElectrical idle diff peak output Voltage change during receiver detection Transmitter Differential Return loss Transmitter Common Mode Return loss DC Differential TX impedance Single ended TX Impedance TX Eye Height (De-emphasized bits) TX Eye Height (Transition bits)
800 -3 -0.1 1
1200 -4 3.7 20 100 25 20 600
mV dB V mV mV mV mV mV dB dB
VTX-CM-DC-linedelta
VTX-Idle-DiffP Serial Link (cont.) VTX-RCV-Detect RLTX-DIFF RLTX-CM ZTX-DEFF-DC ZOSE Transmitter Eye Diagram Transmitter Eye Diagram PCIe Receive VRX-DIFFp-p VRX-CM-AC RLRX-DIFF RLRX-CM ZRX-DIFF-DC ZRX-COMM-DC
12 6 80 40 505 800 100 50 650 950 120 60
mV mV
Differential input voltage (peak-to-peak) Receiver common-mode voltage for AC coupling Receiver Differential Return Loss Receiver Common Mode Return Loss Differential input impedance (DC) Single-ended input impedance
175
1200 150
mV mV dB dB
15 6 80 40 200k 65 100 50 350k 175 120 60
mV
ZRX-COMM-HIGH- Powered down input common mode impedance (DC) Z-DC VRX-IDLE-DETDIFFp-p
Electrical idle detect threshold
PCIe REFCLK CIN Input Capacitance 1.5 -- pF
Table 15 DC Electrical Characteristics (Part 1 of 2)
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IDT 89HPES24NT3 Data Sheet I/O Type Other I/Os LOW Drive Output High Drive Output Schmitt Trigger Input (STI) Input IOL IOH IOL IOH VIL VIH VIL VIH Capacitance Leakage CIN Inputs I/OLEAK W/O Pull-ups/downs I/OLEAK WITH Pull-ups/downs
1.
Parameter
Description
Min1
Typ1
Max1
Unit
Conditions
-- -- -- -- -0.3 2.0 -0.3 2.0 -- -- -- --
2.5 -5.5 12.0 -20.0 -- -- -- -- -- -- -- --
-- -- -- -- 0.8 VDDIO + 0.5 0.8 VDDIO + 0.5 8.5 + 10 + 10 + 80
mA mA mA mA V V V V pF
VOL = 0.4v VOH = 1.5V VOL = 0.4v VOH = 1.5V -- -- -- -- -- VDDI/O (max) VDDI/O (max) VDDI/O (max)
A A A
Table 15 DC Electrical Characteristics (Part 2 of 2)
Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.0a.
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IDT 89HPES24NT3 Data Sheet
Package Pinout -- 420-BGA Signal Pinout for PES24NT3
The following table lists the pin numbers and signal names for the PES24NT3 device.
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 VSS VSS VSS JTAG_TDI JTAG_TMS MSMBADDR_1 MSMBADDR_3 MSMBCLK SSMBADDR_1 SSMBADDR_3 SSMBCLK CCLKUS CCLKDS PEBLREV SWMODE_1 SWMODE_3 PERSTN RSTHALT GPIO_01 GPIO_03 GPIO_05 GPIO_07 VSS VSS VSS VSS VSS VSS VDDIO JTAG_TCK JTAG-TDO JTAG-TRST_N MSMBADDR_2 MSMBADDR_4 1 1 1 Function Alt Pin B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 Function MSMBDAT SSMBADDR_2 SSMBADDR_5 SSMBDAT PEALREV SWMODE_0 SWMODE_2 PECLREV PENTBRSTN GPIO_00 GPIO_02 GPIO_04 GPIO_06 MSMBSMODE REFCLKM VDDIO VSS VSS PEREFCLKN1 VSS VSS VDDCORE VDDIO VSS VDDIO VSS VDDIO VSS VDDIO VSS VDDIO VDDCORE VDDIO VDDCORE 1 1 1 Alt Pin C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 Function VDDIO VSS VDDIO VSS VDDIO VSS VDDIO VSS VSS PEREFCLKP2 PEREFCLKP1 VSS VSS VSS VDDCORE VDDCORE VSS VDDCORE VSS VDDCORE VSS VDDCORE VDDCORE VSS VDDCORE VSS VDDCORE VDDCORE VDDCORE VSS VDDCORE VDDCORE VSS VSS Alt Pin D25 D26 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 F22 VSS PEREFCLKN2 VSS VSS VSS VSS VSS VDDCORE VDDCORE VSS VDDCORE VSS VDDCORE VSS VDDCORE VSS VDDCORE VSS VDDCORE VSS VDDCORE VDDCORE VDDCORE VSS VSS VSS VSS VSS VDDCORE VDDCORE VDDAPE VSS VSS VSS Function Alt
Table 16 PES24NT3 420-pin Signal Pin-Out (Part 1 of 3)
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IDT 89HPES24NT3 Data Sheet Pin F23 F24 F25 F26 G1 G2 G3 G4 G5 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H22 H23 H24 H25 H26 J1 J2 J3 J4 J5 J22 J23 J24 J25 J26 K1 K2 K3 VSS VDDAPE VDDCORE VDDCORE PEBTN07 PEBTP07 VDDPE PEBRN07 PEBRP07 PECRP00 PECRN00 VDDPE PECTP00 PECTN00 VSS VSS VTTPE VTTPE VSS VSS VTTPE VTTPE VSS VSS PEBTN06 PEBTP06 VDDPE PEBRN06 PEBRP06 PECRP01 PECRN01 VDDPE PECTP01 PECTN01 VSS VSS VDDAPE Function Alt Pin K4 K5 K22 K23 K24 K25 K26 L1 L2 L3 L4 L5 L22 L23 L24 L25 L26 M1 M2 M3 M4 M5 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N22 N23 N24 N25 N26 Function VDDAPE VDDAPE VDDAPE VDDAPE VDDAPE VSS VSS PEBTN05 PEBTP05 VDDPE PEBRN05 PEBRP05 PECRP02 PECRN02 VDDPE PECTP02 PECTN02 VDDCORE VSS VTTPE VTTPE VSS VSS VTTPE VTTPE VSS VDDCORE PEBTN04 PEBTP04 VDDPE PEBRN04 PEBRP04 PECRP03 PECRN03 VDDPE PECTP03 PECTN03 Alt Pin P1 P2 P3 P4 P5 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R22 R23 R24 R25 R26 T1 T2 T3 T4 T5 T22 T23 T24 T25 T26 U1 U2 U3 U4 U5 U22 U23 Function VDDCORE VSS VTTPE VTTPE VSS VSS VTTPE VTTPE VSS VDDCORE PEBTN03 PEBTP03 VDDPE PEBRN03 PEBRP03 PECRP04 PECRN04 VDDPE PECTP04 PECTN04 VDDCORE VSS VDDAPE VDDAPE VSS VSS VDDAPE VDDAPE VSS VDDCORE PEBTN02 PEBTP02 VDDPE PEBRN02 PEBRP02 PECRP05 PECRN05 Alt Pin U24 U25 U26 V1 V2 V3 V4 V5 V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y22 Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 Function VDDPE PECTP05 PECTN05 VDDCORE VSS VDDAPE VDDAPE VDDAPE VDDAPE VDDAPE VDDAPE VSS VDDCORE PEBTN01 PEBTP01 VDDPE PEBRN01 PEBRP01 PECRP06 PECRN06 VDDPE PECTP06 PECTN06 VSS VSS VTTPE VTTPE VSS VSS VTTPE VTTPE VSS VSS PEBTN00 PEBTP00 VDDPE PEBRN00 Alt
Table 16 PES24NT3 420-pin Signal Pin-Out (Part 2 of 3)
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IDT 89HPES24NT3 Data Sheet Pin AA5 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 Function PEBRP00 PECRP07 PECRN07 VDDPE PECTP07 PECTN07 VSS VSS VDDCORE VDDCORE VDDCORE VSS PEARP07 VSS PEARP06 VDDAPE PEARP05 VSS PEARP04 VDDAPE PEARP03 VSS PEARP02 VDDAPE PEARP01 VSS PEARP00 VSS VDDCORE VDDCORE VSS VSS VSS VSS Alt Pin AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 Function VDDCORE VDDCORE VDDCORE VTTPE PEARN07 VDDAPE PEARN06 VDDAPE PEARN05 VTTPE PEARN04 VTTPE PEARN03 VDDAPE PEARN02 VDDAPE PEARN01 VTTPE PEARN00 VSS VDDCORE VDDCORE VSS VSS VSS VSS VDDCORE VDDCORE VDDCORE VTTPE VSS VDDPE VSS VDDPE Alt Pin AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 Function VDDPE VTTPE VDDPE VTTPE VDDPE VDDAPE VSS VDDPE VDDPE VTTPE VDDPE VSS VDDCORE VDDCORE VSS VSS VSS VSS VDDCORE VDDCORE VSS VSS PEATP07 VSS PEATP06 VSS PEATP05 VSS PEATP04 VSS PEATP03 VSS PEATP02 VSS Alt Pin AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 Function PEATP01 VSS PEATP00 VSS VDDCORE VDDCORE VSS VSS VSS VSS VDDCORE VDDCORE VDDCORE VSS PEATN07 VSS PEATN06 VDDCORE PEATN05 VDDCORE PEATN04 VDDCORE PEATN03 VDDCORE PEATN02 VSS PEATN01 VSS PEATN00 VSS VDDCORE VDDCORE VSS VSS Alt
Table 16 PES24NT3 420-pin Signal Pin-Out (Part 3 of 3)
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IDT 89HPES24NT3 Data Sheet
Power Pins
VDDCore C4 C14 C16 D5 D6 D8 D10 D12 D13 D15 D17 D18 D19 D21 D22 E6 E7 E9 E11 E13 E15 E17 E19 E20 E21 F1 VDDCore F2 F25 F26 M1 M26 P1 P26 T1 T26 V1 V26 AB3 AB4 AB5 AB23 AB24 AC3 AC4 AC5 AC23 AC24 AD3 AD4 AD5 AD23 AD24 Table 17 PES24NT3 Power Pins VDDCore AE3 AE4 AE23 AE24 AF3 AF4 AF5 AF10 AF12 AF14 AF16 AF23 AF24 VDDIO B3 B24 C5 C7 C9 C11 C13 C15 C17 C19 C21 C23 VDDPE G3 G24 J3 J24 L3 L24 N3 N24 R3 R24 U3 U24 W3 W24 AA3 AA24 AD8 AD10 AD11 AD13 AD15 AD18 AD19 AD21 VDDAPE F3 F24 K3 K4 K5 K22 K23 K24 T3 T4 T23 T24 V3 V4 V5 V22 V23 V24 AB10 AB14 AB18 AC8 AC10 AC16 AC18 AD16 VTTPE H3 H4 H23 H24 M3 M4 M23 M24 P3 P4 P23 P24 Y3 Y4 Y23 Y24 AC6 AC12 AC14 AC20 AD6 AD12 AD14 AD20
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IDT 89HPES24NT3 Data Sheet
Ground Pins
Vss A1 A2 A3 A23 A24 A25 A26 B1 B2 B25 B26 C2 C3 C6 C8 C10 C12 C18 C20 C22 C24 C25 D2 D3 D4 D7 D9 Vss D11 D14 D16 D20 D23 D24 D25 E1 E2 E3 E4 E5 E8 E10 E12 E14 E16 E18 E22 E23 E24 E25 E26 F4 F5 F22 F23 Vss H1 H2 H5 H22 H25 H26 K1 K2 K25 K26 M2 M5 M22 M25 P2 P5 P22 P25 T2 T5 T22 T25 V2 V25 Y1 Y2 Y5 Table 18 PES24NT3 Ground Pins Vss Y22 Y25 Y26 AB1 AB2 AB6 AB8 AB12 AB16 AB20 AB22 AB25 AB26 AC1 AC2 AC22 AC25 AC26 AD1 AD2 AD7 AD9 AD17 AD22 AD25 AD26 AE1 Vss AE2 AE5 AE6 AE8 AE10 AE12 AE14 AE16 AE18 AE20 AE22 AE25 AE26 AF1 AF2 AF6 AF8 AF18 AF20 AF22 AF25 AF26
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IDT 89HPES24NT3 Data Sheet
Alternate Signal Functions
Pin B18 A19 B19 A20 B20 A21 GPIO GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] Alternate PEBRSTN PECRSTN PALINKUPN PBLINKUPN PCLINKUPN FAILOVERP
Table 19 PES24NT3 Alternate Signal Functions
Signals Listed Alphabetically
Signal Name CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07 JTAG_TCK JTAG_TDI JTAG_TMS JTAG-TDO JTAG-TRST_N MSMBADDR_1 MSMBADDR_2 MSMBADDR_3 MSMBADDR_4 MSMBCLK MSMBDAT MSMBSMODE I/O Type I I I/O I/O I/O I/O I/O I/O I/O I/O I I I O I I I I I I/O I/O I Location A13 A12 B18 A19 B19 A20 B20 A21 B21 A22 B4 A4 A5 B5 B6 A6 B7 A7 B8 A8 B9 B22 System SMBus JTAG General Purpose Input/Output Signal Category System
Table 20 89PES24NT3 Alphabetical Signal List (Part 1 of 5)
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IDT 89HPES24NT3 Data Sheet Signal Name PEALREV PEARN00 PEARN01 PEARN02 PEARN03 PEARN04 PEARN05 PEARN06 PEARN07 PEARP00 PEARP01 PEARP02 PEARP03 PEARP04 PEARP05 PEARP06 PEARP07 PEATN00 PEATN01 PEATN02 PEATN03 PEATN04 PEATN05 PEATN06 PEATN07 PEATP00 PEATP01 PEATP02 PEATP03 PEATP04 PEATP05 PEATP06 PEATP07 PEBLREV PEBRN00 PEBRN01 I/O Type I I I I I I I I I I I I I I I I I O O O O O O O O O O O O O O O O I I I Location B13 AC21 AC19 AC17 AC15 AC13 AC11 AC9 AC7 AB21 AB19 AB17 AB15 AB13 AB11 AB9 AB7 AF21 AF19 AF17 AF15 AF13 AF11 AF9 AF7 AE21 AE19 AE17 AE15 AE13 AE11 AE9 AE7 A14 AA4 W4 Signal Category PCI Express
Table 20 89PES24NT3 Alphabetical Signal List (Part 2 of 5)
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IDT 89HPES24NT3 Data Sheet Signal Name PEBRN02 PEBRN03 PEBRN04 PEBRN05 PEBRN06 PEBRN07 PEBRP00 PEBRP01 PEBRP02 PEBRP03 PEBRP04 PEBRP05 PEBRP06 PEBRP07 PEBTN00 PEBTN01 PEBTN02 PEBTN03 PEBTN04 PEBTN05 PEBTN06 PEBTN07 PEBTP00 PEBTP01 PEBTP02 PEBTP03 PEBTP04 PEBTP05 PEBTP06 PEBTP07 PECLREV PECRN00 PECRN01 PECRN02 PECRN03 PECRN04 I/O Type I I I I I I I I I I I I I I O O O O O O O O O O O O O O O O I I I I I I Location U4 R4 N4 L4 J4 G4 AA5 W5 U5 R5 N5 L5 J5 G5 AA1 W1 U1 R1 N1 L1 J1 G1 AA2 W2 U2 R2 N2 L2 J2 G2 B16 G23 J23 L23 N23 R23 Signal Category PCI Express
Table 20 89PES24NT3 Alphabetical Signal List (Part 3 of 5)
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IDT 89HPES24NT3 Data Sheet Signal Name PECRN05 PECRN06 PECRN07 PECRP00 PECRP01 PECRP02 PECRP03 PECRP04 PECRP05 PECRP06 PECRP07 PECTN00 PECTN01 PECTN02 PECTN03 PECTN04 PECTN05 PECTN06 PECTN07 PECTP00 PECTP01 PECTP02 PECTP03 PECTP04 PECTP05 PECTP06 PECTP07 PENTBRSTN PEREFCLKN1 PEREFCLKN2 PEREFCLKP1 PEREFCLKP2 PERSTN REFCLKM RSTHALT I/O Type I I I I I I I I I I I O O O O O O O O O O O O O O O O I I I I I I I I Location U23 W23 AA23 G22 J22 L22 N22 R22 U22 W22 AA22 G26 J26 L26 N26 R26 U26 W26 AA26 G25 J25 L25 N25 R25 U25 W25 AA25 B17 C1 D26 D1 C26 A17 B23 A18 System PCI Express System System PCI Express Signal Category PCI Express
Table 20 89PES24NT3 Alphabetical Signal List (Part 4 of 5)
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IDT 89HPES24NT3 Data Sheet Signal Name SSMBADDR_1 SSMBADDR_2 SSMBADDR_3 SSMBADDR_5 SSMBCLK SSMBDAT SWMODE_0 SWMODE_1 SWMODE_2 SWMODE_3 VDDCORE, VDDAPE, VDDIO, VDDPE, VTTPE VSS I/O Type I I I I I/O I/O I I I I Location A9 B10 A10 B11 A11 B12 B14 A15 B15 A16 System System SMBus Signal Category SMBus
See Table 17 for a listing of power pins.
See Table 18 for a listing of ground pins. Table 20 89PES24NT3 Alphabetical Signal List (Part 5 of 5)
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IDT 89HPES24NT3 Data Sheet
PES24NT3 Pinout -- Top View
1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF VDDCore (Power) VDDI/O (Power) 2 3 4 5 6 78 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
xx
xx
xx xx
xx xx
xx x x x x x x x x
xx
x
VTTPE (Power) VDDPE (Power) VDDAPE (Power)
Vss (Ground)
Signals
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IDT 89HPES24NT3 Data Sheet
PES24NT3 Package Drawing -- 420-Pin BX420/BXG420
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IDT 89HPES24NT3 Data Sheet
PES24NT3 Package Drawing -- Page Two
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IDT 89HPES24NT3 Data Sheet
Revision History
March 15, 2007: Initial publication of Preliminary data sheet. April 11, 2007: In Table 2, revised description of MSMBCLK.
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IDT 89HPES24NT3 Data Sheet
Ordering Information
NN Product Family A Operating Voltage AAA Device Family NNAN Product Detail AA Revision ID AA Package A Temp Range Legend A = Alpha Character N = Numeric Character
Blank
Commercial Temperature (0C to +70C Ambient) BX420 420-ball BGA BXG420 420-ball BGA, Green
BX BXG ZA
Silicon revision
24NT3
24-lane, 3-port Non-Transparent PCI Express Switch
PES
H 89
1.0V +/- 0.1V Core Voltage Serial Switching Product
Valid Combinations
89HPES24NT3ZABX 89HPES24NT3ZABXG 420-pin BX420 package, Commercial Temperature 420-pin Green BX420 package, Commercial Temperature
(R)
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